1. Field of the Invention
The present invention relates generally to improper bit combination detection circuits and, in particular, to circuits in an asynchronous data reception device for flagging the occurrence of a variety of bit errors in sequentially transmitted parallel data bytes.
2. Prior Art
Copending patent application Ser. No. 07/286,196 of the present inventor filed Dec. 19, 1988 provides a Power-Up Synchronization circuit for synchronizing parallel transferred data words to the timing within a data reception device. The present invention as taught herein may be used in cooperaton with the structure claimed in U.S. Pat. No. 4,885,583 dated Dec. 5, 1989 of John McCambridge entitled "Serial to Parallel Data Conversion System".
In bus data transmission systems, where a transmitter sends messages over a bus to multiple receivers connected to the bus, normally the basic elements of a communication protocol exist. Usually there exist a set of symbols or character sets, a set of rules for the sequence and timing of messages constructed from the character set and procedures for determining when an error has occurred in the transmission and how to correct the error. The character set usually consists of a subset which is meaningful to the parties communicating (printing character - name) and another subset which conveys control information meaningful to the processing equipment (control characters - symbol). A correspondence exists between the name and the symbol; e.g., the name "fuel" corresponds to code 0000, "speed" corresponds to the code 0110. The set of rules followed by the sender and receiver gives the meaning, permissible sequence, and time relationships of the printing names and the control symbols. The error detection and correction procedures allows for the detection of orderly recovery from errors caused by factors outside the control of the sending and receiving devices.
For asynchronous data, encoded symbols for the start and stop of a message provides control for synchronizing receipt to the transmission of the data.
For the purpose of error detection, an added encoded parity symbol to the transmitted message permits the receiver to provide an indication to the sender of the occurrences of uneven parities.
Another technique, where the receiver echoes symbols back to the sender, provides another form of protocol that lets the sender know if the correct data reaches the receiver.
Still another technique, checksums, provide a measure of confidences in the transmitted messages. There, a binary addition technique achieves a redundancy check of symbols of the message for detecting single and multiple bit errors usually in synchronous systems.
A problem exists in data reception devices having no special timing signal (asynchronous systems) adapted to function with synchronous systems for detecting improper bits. A search for various schemes for detecting improper bits in stand alone data reception devices was initiated. The search resulted in the improper bit detection circuit of the present invention.